Gecko [ www.foryou-vip.com ]

Name	Size	Permission	Date
android	[ DIR ]	drwxrwxrwx	2024-03-12 22:00
byteorder	[ DIR ]	drwxrwxrwx	2024-03-12 22:00
caif	[ DIR ]	drwxrwxrwx	2024-03-12 22:00
can	[ DIR ]	drwxrwxrwx	2024-03-12 22:00
cifs	[ DIR ]	drwxr-xr-x	2024-03-12 22:00
dvb	[ DIR ]	drwxrwxrwx	2024-03-12 22:00
genwqe	[ DIR ]	drwxr-xr-x	2024-03-12 22:00
hdlc	[ DIR ]	drwxrwxrwx	2024-03-12 22:00
hsi	[ DIR ]	drwxrwxrwx	2024-03-12 22:00
iio	[ DIR ]	drwxrwxrwx	2024-03-12 22:00
isdn	[ DIR ]	drwxrwxrwx	2024-03-12 22:00
mmc	[ DIR ]	drwxrwxrwx	2024-03-12 22:00
netfilter	[ DIR ]	drwxrwxrwx	2024-03-12 22:00
netfilter_arp	[ DIR ]	drwxrwxrwx	2024-03-12 22:00
netfilter_bridge	[ DIR ]	drwxrwxrwx	2024-03-12 22:00
netfilter_ipv4	[ DIR ]	drwxrwxrwx	2024-03-12 22:00
netfilter_ipv6	[ DIR ]	drwxrwxrwx	2024-03-12 22:00
nfsd	[ DIR ]	drwxrwxrwx	2024-03-12 22:00
raid	[ DIR ]	drwxrwxrwx	2024-03-12 22:00
spi	[ DIR ]	drwxrwxrwx	2024-03-12 22:00
sunrpc	[ DIR ]	drwxrwxrwx	2024-03-12 22:00
tc_act	[ DIR ]	drwxrwxrwx	2024-03-12 22:00
tc_ematch	[ DIR ]	drwxrwxrwx	2024-03-12 22:00
usb	[ DIR ]	drwxrwxrwx	2024-03-12 22:00
wimax	[ DIR ]	drwxrwxrwx	2024-03-12 22:00
a.out.h	7.15 KB	-rw-r--r--	2022-06-30 20:26
acct.h	3.58 KB	-rw-r--r--	2022-06-30 20:26
adb.h	1.05 KB	-rw-r--r--	2022-06-30 20:26
adfs_fs.h	873 B	-rw-r--r--	2022-06-30 20:26
affs_hardblocks.h	1.45 KB	-rw-r--r--	2022-06-30 20:26
agpgart.h	3.85 KB	-rw-r--r--	2022-06-30 20:26
aio_abi.h	3.1 KB	-rw-r--r--	2022-06-30 20:26
am437x-vpfe.h	3.53 KB	-rw-r--r--	2022-06-30 20:26
apm_bios.h	3.53 KB	-rw-r--r--	2022-06-30 20:26
arcfb.h	150 B	-rw-r--r--	2022-06-30 20:26
atalk.h	960 B	-rw-r--r--	2022-06-30 20:26
atm.h	7.64 KB	-rw-r--r--	2022-06-30 20:26
atm_eni.h	585 B	-rw-r--r--	2022-06-30 20:26
atm_he.h	343 B	-rw-r--r--	2022-06-30 20:26
atm_idt77105.h	892 B	-rw-r--r--	2022-06-30 20:26
atm_nicstar.h	1.19 KB	-rw-r--r--	2022-06-30 20:26
atm_tcp.h	1.52 KB	-rw-r--r--	2022-06-30 20:26
atm_zatm.h	1.44 KB	-rw-r--r--	2022-06-30 20:26
atmapi.h	889 B	-rw-r--r--	2022-06-30 20:26
atmarp.h	1.2 KB	-rw-r--r--	2022-06-30 20:26
atmbr2684.h	3.13 KB	-rw-r--r--	2022-06-30 20:26
atmclip.h	513 B	-rw-r--r--	2022-06-30 20:26
atmdev.h	7.44 KB	-rw-r--r--	2022-06-30 20:26
atmioc.h	1.55 KB	-rw-r--r--	2022-06-30 20:26
atmlec.h	2.26 KB	-rw-r--r--	2022-06-30 20:26
atmmpc.h	4.07 KB	-rw-r--r--	2022-06-30 20:26
atmppp.h	576 B	-rw-r--r--	2022-06-30 20:26
atmsap.h	4.79 KB	-rw-r--r--	2022-06-30 20:26
atmsvc.h	1.75 KB	-rw-r--r--	2022-06-30 20:26
audit.h	18.44 KB	-rw-r--r--	2022-06-30 20:26
auto_dev-ioctl.h	4.96 KB	-rw-r--r--	2022-06-30 20:26
auto_fs.h	2.15 KB	-rw-r--r--	2022-06-30 20:26
auto_fs4.h	3.95 KB	-rw-r--r--	2022-06-30 20:26
auxvec.h	1.4 KB	-rw-r--r--	2022-06-30 20:26
ax25.h	2.7 KB	-rw-r--r--	2022-06-30 20:26
b1lli.h	1.62 KB	-rw-r--r--	2022-06-30 20:26
baycom.h	820 B	-rw-r--r--	2022-06-30 20:26
bcache.h	8.11 KB	-rw-r--r--	2022-06-30 20:26
bcm933xx_hcs.h	356 B	-rw-r--r--	2022-06-30 20:26
bfs_fs.h	1.79 KB	-rw-r--r--	2022-06-30 20:26
binfmts.h	565 B	-rw-r--r--	2022-06-30 20:26
blkpg.h	1.53 KB	-rw-r--r--	2022-06-30 20:26
blktrace_api.h	4.38 KB	-rw-r--r--	2022-06-30 20:26
bpf.h	14.31 KB	-rw-r--r--	2022-06-30 20:26
bpf_common.h	1.2 KB	-rw-r--r--	2022-06-30 20:26
bpf_perf_event.h	468 B	-rw-r--r--	2022-06-30 20:26
bpqether.h	918 B	-rw-r--r--	2022-06-30 20:26
bsg.h	2.37 KB	-rw-r--r--	2022-06-30 20:26
bt-bmc.h	508 B	-rw-r--r--	2022-06-30 20:26
btrfs.h	25.29 KB	-rw-r--r--	2022-06-30 20:26
btrfs_tree.h	24.56 KB	-rw-r--r--	2022-06-30 20:26
can.h	7.62 KB	-rw-r--r--	2022-06-30 20:26
capability.h	11.07 KB	-rw-r--r--	2022-06-30 20:26
capi.h	2.99 KB	-rw-r--r--	2022-06-30 20:26
cciss_defs.h	3.14 KB	-rw-r--r--	2022-06-30 20:26
cciss_ioctl.h	2.63 KB	-rw-r--r--	2022-06-30 20:26
cdrom.h	28.12 KB	-rw-r--r--	2022-06-30 20:26
cgroupstats.h	2.1 KB	-rw-r--r--	2022-06-30 20:26
chio.h	5.16 KB	-rw-r--r--	2022-06-30 20:26
cm4000_cs.h	1.7 KB	-rw-r--r--	2022-06-30 20:26
cn_proc.h	3.19 KB	-rw-r--r--	2022-06-30 20:26
coda.h	17.09 KB	-rw-r--r--	2022-06-30 20:26
coda_psdev.h	297 B	-rw-r--r--	2022-06-30 20:26
coff.h	12.12 KB	-rw-r--r--	2022-06-30 20:26
connector.h	2.14 KB	-rw-r--r--	2022-06-30 20:26
const.h	872 B	-rw-r--r--	2022-06-30 20:26
coresight-stm.h	643 B	-rw-r--r--	2022-06-30 20:26
cramfs_fs.h	2.68 KB	-rw-r--r--	2022-06-30 20:26
cryptouser.h	3.17 KB	-rw-r--r--	2022-06-30 20:26
cuda.h	842 B	-rw-r--r--	2022-06-30 20:26
cyclades.h	16.65 KB	-rw-r--r--	2022-06-30 20:26
cycx_cfm.h	2.86 KB	-rw-r--r--	2022-06-30 20:26
dcbnl.h	24.27 KB	-rw-r--r--	2022-06-30 20:26
dccp.h	6.22 KB	-rw-r--r--	2022-06-30 20:26
devlink.h	4.12 KB	-rw-r--r--	2022-06-30 20:26
dlm.h	2.43 KB	-rw-r--r--	2022-06-30 20:26
dlm_device.h	2.42 KB	-rw-r--r--	2022-06-30 20:26
dlm_netlink.h	1.04 KB	-rw-r--r--	2022-06-30 20:26
dlm_plock.h	831 B	-rw-r--r--	2022-06-30 20:26
dlmconstants.h	4.9 KB	-rw-r--r--	2022-06-30 20:26
dm-ioctl.h	10.45 KB	-rw-r--r--	2022-06-30 20:26
dm-log-userspace.h	14.82 KB	-rw-r--r--	2022-06-30 20:26
dn.h	4.47 KB	-rw-r--r--	2022-06-30 20:26
dqblk_xfs.h	8.72 KB	-rw-r--r--	2022-06-30 20:26
edd.h	5.41 KB	-rw-r--r--	2022-06-30 20:26
efs_fs_sb.h	2.11 KB	-rw-r--r--	2022-06-30 20:26
elf-em.h	2.12 KB	-rw-r--r--	2022-06-30 20:26
elf-fdpic.h	1.04 KB	-rw-r--r--	2022-06-30 20:26
elf.h	12.59 KB	-rw-r--r--	2022-06-30 20:26
elfcore.h	2.86 KB	-rw-r--r--	2022-06-30 20:26
errno.h	23 B	-rw-r--r--	2022-06-30 20:26
errqueue.h	1.21 KB	-rw-r--r--	2022-06-30 20:26
ethtool.h	67.51 KB	-rw-r--r--	2022-06-30 20:26
eventpoll.h	2.42 KB	-rw-r--r--	2022-06-30 20:26
fadvise.h	779 B	-rw-r--r--	2022-06-30 20:26
falloc.h	3.44 KB	-rw-r--r--	2022-06-30 20:26
fanotify.h	3.42 KB	-rw-r--r--	2022-06-30 20:26
fb.h	16 KB	-rw-r--r--	2022-06-30 20:26
fcntl.h	2.16 KB	-rw-r--r--	2022-06-30 20:26
fd.h	11.34 KB	-rw-r--r--	2022-06-30 20:26
fdreg.h	5.23 KB	-rw-r--r--	2022-06-30 20:26
fib_rules.h	1.64 KB	-rw-r--r--	2022-06-30 20:26
fiemap.h	2.65 KB	-rw-r--r--	2022-06-30 20:26
filter.h	2.1 KB	-rw-r--r--	2022-06-30 20:26
firewire-cdev.h	42.86 KB	-rw-r--r--	2022-06-30 20:26
firewire-constants.h	3.16 KB	-rw-r--r--	2022-06-30 20:26
flat.h	2.04 KB	-rw-r--r--	2022-06-30 20:26
fou.h	631 B	-rw-r--r--	2022-06-30 20:26
fs.h	13.2 KB	-rw-r--r--	2022-06-30 20:26
fsl_hypervisor.h	7.05 KB	-rw-r--r--	2022-06-30 20:26
fuse.h	16.98 KB	-rw-r--r--	2022-06-30 20:26
futex.h	4.81 KB	-rw-r--r--	2022-06-30 20:26
gameport.h	834 B	-rw-r--r--	2022-06-30 20:26
gen_stats.h	1.48 KB	-rw-r--r--	2022-06-30 20:26
genetlink.h	1.77 KB	-rw-r--r--	2022-06-30 20:26
gfs2_ondisk.h	12 KB	-rw-r--r--	2022-06-30 20:26
gigaset_dev.h	1.35 KB	-rw-r--r--	2022-06-30 20:26
gpio.h	5.55 KB	-rw-r--r--	2022-06-30 20:26
gsmmux.h	978 B	-rw-r--r--	2022-06-30 20:26
gtp.h	499 B	-rw-r--r--	2022-06-30 20:26
hash_info.h	857 B	-rw-r--r--	2022-06-30 20:26
hdlc.h	574 B	-rw-r--r--	2022-06-30 20:26
hdlcdrv.h	2.78 KB	-rw-r--r--	2022-06-30 20:26
hdreg.h	22.11 KB	-rw-r--r--	2022-06-30 20:26
hid.h	1.79 KB	-rw-r--r--	2022-06-30 20:26
hiddev.h	6.13 KB	-rw-r--r--	2022-06-30 20:26
hidraw.h	1.41 KB	-rw-r--r--	2022-06-30 20:26
hpet.h	680 B	-rw-r--r--	2022-06-30 20:26
hsr_netlink.h	1017 B	-rw-r--r--	2022-06-30 20:26
hw_breakpoint.h	575 B	-rw-r--r--	2022-06-30 20:26
hyperv.h	10.26 KB	-rw-r--r--	2022-06-30 20:26
hysdn_if.h	1.29 KB	-rw-r--r--	2022-06-30 20:26
i2c-dev.h	2.49 KB	-rw-r--r--	2022-06-30 20:26
i2c.h	6.74 KB	-rw-r--r--	2022-06-30 20:26
i2o-dev.h	11.22 KB	-rw-r--r--	2022-06-30 20:26
i8k.h	1.43 KB	-rw-r--r--	2022-06-30 20:26
icmp.h	2.84 KB	-rw-r--r--	2022-06-30 20:26
icmpv6.h	3.82 KB	-rw-r--r--	2022-06-30 20:26
if.h	10.44 KB	-rw-r--r--	2022-06-30 20:26
if_addr.h	1.7 KB	-rw-r--r--	2022-06-30 20:26
if_addrlabel.h	658 B	-rw-r--r--	2022-06-30 20:26
if_alg.h	882 B	-rw-r--r--	2022-06-30 20:26
if_arcnet.h	3.57 KB	-rw-r--r--	2022-06-30 20:26
if_arp.h	6.24 KB	-rw-r--r--	2022-06-30 20:26
if_bonding.h	4.11 KB	-rw-r--r--	2022-06-30 20:26
if_bridge.h	6.22 KB	-rw-r--r--	2022-06-30 20:26
if_cablemodem.h	922 B	-rw-r--r--	2022-06-30 20:26
if_eql.h	1.26 KB	-rw-r--r--	2022-06-30 20:26
if_ether.h	7.27 KB	-rw-r--r--	2022-06-30 20:26
if_fc.h	1.63 KB	-rw-r--r--	2022-06-30 20:26
if_fddi.h	3.6 KB	-rw-r--r--	2022-06-30 20:26
if_frad.h	2.89 KB	-rw-r--r--	2022-06-30 20:26
if_hippi.h	4.07 KB	-rw-r--r--	2022-06-30 20:26
if_infiniband.h	1.13 KB	-rw-r--r--	2022-06-30 20:26
if_link.h	20 KB	-rw-r--r--	2022-06-30 20:26
if_ltalk.h	147 B	-rw-r--r--	2022-06-30 20:26
if_macsec.h	5.42 KB	-rw-r--r--	2022-06-30 20:26
if_packet.h	7.63 KB	-rw-r--r--	2022-06-30 20:26
if_phonet.h	361 B	-rw-r--r--	2022-06-30 20:26
if_plip.h	596 B	-rw-r--r--	2022-06-30 20:26
if_ppp.h	29 B	-rw-r--r--	2022-06-30 20:26
if_pppol2tp.h	3.15 KB	-rw-r--r--	2022-06-30 20:26
if_pppox.h	4.7 KB	-rw-r--r--	2022-06-30 20:26
if_slip.h	809 B	-rw-r--r--	2022-06-30 20:26
if_team.h	2.48 KB	-rw-r--r--	2022-06-30 20:26
if_tun.h	3.72 KB	-rw-r--r--	2022-06-30 20:26
if_tunnel.h	3.44 KB	-rw-r--r--	2022-06-30 20:26
if_vlan.h	1.69 KB	-rw-r--r--	2022-06-30 20:26
if_x25.h	817 B	-rw-r--r--	2022-06-30 20:26
igmp.h	2.88 KB	-rw-r--r--	2022-06-30 20:26
ila.h	760 B	-rw-r--r--	2022-06-30 20:26
in.h	9.38 KB	-rw-r--r--	2022-06-30 20:26
in6.h	7.15 KB	-rw-r--r--	2022-06-30 20:26
in_route.h	873 B	-rw-r--r--	2022-06-30 20:26
inet_diag.h	3.41 KB	-rw-r--r--	2022-06-30 20:26
inotify.h	2.85 KB	-rw-r--r--	2022-06-30 20:26
input-event-codes.h	23.87 KB	-rw-r--r--	2022-06-30 20:26
input.h	14.77 KB	-rw-r--r--	2022-06-30 20:26
ioctl.h	100 B	-rw-r--r--	2022-06-30 20:26
ip.h	4.53 KB	-rw-r--r--	2022-06-30 20:26
ip6_tunnel.h	1.67 KB	-rw-r--r--	2022-06-30 20:26
ip_vs.h	13.25 KB	-rw-r--r--	2022-06-30 20:26
ipc.h	1.99 KB	-rw-r--r--	2022-06-30 20:26
ipmi.h	15.8 KB	-rw-r--r--	2022-06-30 20:26
ipmi_msgdefs.h	4.37 KB	-rw-r--r--	2022-06-30 20:26
ipsec.h	884 B	-rw-r--r--	2022-06-30 20:26
ipv6.h	3.58 KB	-rw-r--r--	2022-06-30 20:26
ipv6_route.h	1.73 KB	-rw-r--r--	2022-06-30 20:26
ipx.h	2.23 KB	-rw-r--r--	2022-06-30 20:26
irda.h	7.31 KB	-rw-r--r--	2022-06-30 20:26
irqnr.h	104 B	-rw-r--r--	2022-06-30 20:26
isdn.h	5.58 KB	-rw-r--r--	2022-06-30 20:26
isdn_divertif.h	1.11 KB	-rw-r--r--	2022-06-30 20:26
isdn_ppp.h	1.82 KB	-rw-r--r--	2022-06-30 20:26
isdnif.h	2.25 KB	-rw-r--r--	2022-06-30 20:26
iso_fs.h	6.29 KB	-rw-r--r--	2022-06-30 20:26
ivtv.h	2.89 KB	-rw-r--r--	2022-06-30 20:26
ivtvfb.h	1.12 KB	-rw-r--r--	2022-06-30 20:26
ixjuser.h	24.53 KB	-rw-r--r--	2022-06-30 20:26
jffs2.h	6.85 KB	-rw-r--r--	2022-06-30 20:26
joystick.h	3.5 KB	-rw-r--r--	2022-06-30 20:26
kcm.h	759 B	-rw-r--r--	2022-06-30 20:26
kcmp.h	214 B	-rw-r--r--	2022-06-30 20:26
kcov.h	247 B	-rw-r--r--	2022-06-30 20:26
kd.h	6.04 KB	-rw-r--r--	2022-06-30 20:26
kdev_t.h	320 B	-rw-r--r--	2022-06-30 20:26
kernel-page-flags.h	814 B	-rw-r--r--	2022-06-30 20:26
kernel.h	131 B	-rw-r--r--	2022-06-30 20:26
kernelcapi.h	956 B	-rw-r--r--	2022-06-30 20:26
kexec.h	1.73 KB	-rw-r--r--	2022-06-30 20:26
keyboard.h	12.42 KB	-rw-r--r--	2022-06-30 20:26
keyctl.h	3.17 KB	-rw-r--r--	2022-06-30 20:26
kfd_ioctl.h	8.62 KB	-rw-r--r--	2022-06-30 20:26
kvm.h	37.19 KB	-rw-r--r--	2022-06-30 20:26
kvm_para.h	760 B	-rw-r--r--	2022-06-30 20:26
l2tp.h	5.44 KB	-rw-r--r--	2022-06-30 20:26
libc-compat.h	8.03 KB	-rw-r--r--	2022-06-30 20:26
lightnvm.h	3.69 KB	-rw-r--r--	2022-06-30 20:26
limits.h	874 B	-rw-r--r--	2022-06-30 20:26
lirc.h	4.88 KB	-rw-r--r--	2022-06-30 20:26
llc.h	2.98 KB	-rw-r--r--	2022-06-30 20:26
loop.h	2.36 KB	-rw-r--r--	2022-06-30 20:26
lp.h	3.72 KB	-rw-r--r--	2022-06-30 20:26
lwtunnel.h	811 B	-rw-r--r--	2022-06-30 20:26
magic.h	3.12 KB	-rw-r--r--	2022-06-30 20:26
major.h	4.53 KB	-rw-r--r--	2022-06-30 20:26
map_to_7segment.h	7.02 KB	-rw-r--r--	2022-06-30 20:26
matroxfb.h	1.37 KB	-rw-r--r--	2022-06-30 20:26
mdio.h	13.74 KB	-rw-r--r--	2022-06-30 20:26
media-bus-format.h	5.81 KB	-rw-r--r--	2022-06-30 20:26
media.h	11.95 KB	-rw-r--r--	2022-06-30 20:26
mei.h	4.62 KB	-rw-r--r--	2022-06-30 20:26
membarrier.h	2.38 KB	-rw-r--r--	2022-06-30 20:26
memfd.h	186 B	-rw-r--r--	2022-06-30 20:26
mempolicy.h	2.35 KB	-rw-r--r--	2022-06-30 20:26
meye.h	2.41 KB	-rw-r--r--	2022-06-30 20:26
mic_common.h	6.3 KB	-rw-r--r--	2022-06-30 20:26
mic_ioctl.h	2.14 KB	-rw-r--r--	2022-06-30 20:26
mii.h	7.83 KB	-rw-r--r--	2022-06-30 20:26
minix_fs.h	2.01 KB	-rw-r--r--	2022-06-30 20:26
mman.h	230 B	-rw-r--r--	2022-06-30 20:26
mmtimer.h	2.01 KB	-rw-r--r--	2022-06-30 20:26
module.h	192 B	-rw-r--r--	2022-06-30 20:26
mpls.h	1.38 KB	-rw-r--r--	2022-06-30 20:26
mpls_iptunnel.h	650 B	-rw-r--r--	2022-06-30 20:26
mqueue.h	2.06 KB	-rw-r--r--	2022-06-30 20:26
mroute.h	4.06 KB	-rw-r--r--	2022-06-30 20:26
mroute6.h	4.14 KB	-rw-r--r--	2022-06-30 20:26
msdos_fs.h	6.74 KB	-rw-r--r--	2022-06-30 20:26
msg.h	3.21 KB	-rw-r--r--	2022-06-30 20:26
mtio.h	7.92 KB	-rw-r--r--	2022-06-30 20:26
n_r3964.h	2.29 KB	-rw-r--r--	2022-06-30 20:26
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Rename

/*
 * include/linux/serial_reg.h
 *
 * Copyright (C) 1992, 1994 by Theodore Ts'o.
 * 
 * Redistribution of this file is permitted under the terms of the GNU 
 * Public License (GPL)
 * 
 * These are the UART port assignments, expressed as offsets from the base
 * register.  These assignments should hold for any serial port based on
 * a 8250, 16450, or 16550(A).
 */

#ifndef _LINUX_SERIAL_REG_H
#define _LINUX_SERIAL_REG_H

/*
 * DLAB=0
 */
#define UART_RX		0	/* In:  Receive buffer */
#define UART_TX		0	/* Out: Transmit buffer */

#define UART_IER	1	/* Out: Interrupt Enable Register */
#define UART_IER_MSI		0x08 /* Enable Modem status interrupt */
#define UART_IER_RLSI		0x04 /* Enable receiver line status interrupt */
#define UART_IER_THRI		0x02 /* Enable Transmitter holding register int. */
#define UART_IER_RDI		0x01 /* Enable receiver data interrupt */
/*
 * Sleep mode for ST16650 and TI16750.  For the ST16650, EFR[4]=1
 */
#define UART_IERX_SLEEP		0x10 /* Enable sleep mode */

#define UART_IIR	2	/* In:  Interrupt ID Register */
#define UART_IIR_NO_INT		0x01 /* No interrupts pending */
#define UART_IIR_ID		0x0e /* Mask for the interrupt ID */
#define UART_IIR_MSI		0x00 /* Modem status interrupt */
#define UART_IIR_THRI		0x02 /* Transmitter holding register empty */
#define UART_IIR_RDI		0x04 /* Receiver data interrupt */
#define UART_IIR_RLSI		0x06 /* Receiver line status interrupt */

#define UART_IIR_BUSY		0x07 /* DesignWare APB Busy Detect */

#define UART_IIR_RX_TIMEOUT	0x0c /* OMAP RX Timeout interrupt */
#define UART_IIR_XOFF		0x10 /* OMAP XOFF/Special Character */
#define UART_IIR_CTS_RTS_DSR	0x20 /* OMAP CTS/RTS/DSR Change */

#define UART_FCR	2	/* Out: FIFO Control Register */
#define UART_FCR_ENABLE_FIFO	0x01 /* Enable the FIFO */
#define UART_FCR_CLEAR_RCVR	0x02 /* Clear the RCVR FIFO */
#define UART_FCR_CLEAR_XMIT	0x04 /* Clear the XMIT FIFO */
#define UART_FCR_DMA_SELECT	0x08 /* For DMA applications */
/*
 * Note: The FIFO trigger levels are chip specific:
 *	RX:76 = 00  01  10  11	TX:54 = 00  01  10  11
 * PC16550D:	 1   4   8  14		xx  xx  xx  xx
 * TI16C550A:	 1   4   8  14          xx  xx  xx  xx
 * TI16C550C:	 1   4   8  14          xx  xx  xx  xx
 * ST16C550:	 1   4   8  14		xx  xx  xx  xx
 * ST16C650:	 8  16  24  28		16   8  24  30	PORT_16650V2
 * NS16C552:	 1   4   8  14		xx  xx  xx  xx
 * ST16C654:	 8  16  56  60		 8  16  32  56	PORT_16654
 * TI16C750:	 1  16  32  56		xx  xx  xx  xx	PORT_16750
 * TI16C752:	 8  16  56  60		 8  16  32  56
 * OX16C950:	16  32 112 120		16  32  64 112	PORT_16C950
 * Tegra:	 1   4   8  14		16   8   4   1	PORT_TEGRA
 */
#define UART_FCR_R_TRIG_00	0x00
#define UART_FCR_R_TRIG_01	0x40
#define UART_FCR_R_TRIG_10	0x80
#define UART_FCR_R_TRIG_11	0xc0
#define UART_FCR_T_TRIG_00	0x00
#define UART_FCR_T_TRIG_01	0x10
#define UART_FCR_T_TRIG_10	0x20
#define UART_FCR_T_TRIG_11	0x30

#define UART_FCR_TRIGGER_MASK	0xC0 /* Mask for the FIFO trigger range */
#define UART_FCR_TRIGGER_1	0x00 /* Mask for trigger set at 1 */
#define UART_FCR_TRIGGER_4	0x40 /* Mask for trigger set at 4 */
#define UART_FCR_TRIGGER_8	0x80 /* Mask for trigger set at 8 */
#define UART_FCR_TRIGGER_14	0xC0 /* Mask for trigger set at 14 */
/* 16650 definitions */
#define UART_FCR6_R_TRIGGER_8	0x00 /* Mask for receive trigger set at 1 */
#define UART_FCR6_R_TRIGGER_16	0x40 /* Mask for receive trigger set at 4 */
#define UART_FCR6_R_TRIGGER_24  0x80 /* Mask for receive trigger set at 8 */
#define UART_FCR6_R_TRIGGER_28	0xC0 /* Mask for receive trigger set at 14 */
#define UART_FCR6_T_TRIGGER_16	0x00 /* Mask for transmit trigger set at 16 */
#define UART_FCR6_T_TRIGGER_8	0x10 /* Mask for transmit trigger set at 8 */
#define UART_FCR6_T_TRIGGER_24  0x20 /* Mask for transmit trigger set at 24 */
#define UART_FCR6_T_TRIGGER_30	0x30 /* Mask for transmit trigger set at 30 */
#define UART_FCR7_64BYTE	0x20 /* Go into 64 byte mode (TI16C750 and
					some Freescale UARTs) */

#define UART_FCR_R_TRIG_SHIFT		6
#define UART_FCR_R_TRIG_BITS(x)		\
	(((x) & UART_FCR_TRIGGER_MASK) >> UART_FCR_R_TRIG_SHIFT)
#define UART_FCR_R_TRIG_MAX_STATE	4

#define UART_LCR	3	/* Out: Line Control Register */
/*
 * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting 
 * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
 */
#define UART_LCR_DLAB		0x80 /* Divisor latch access bit */
#define UART_LCR_SBC		0x40 /* Set break control */
#define UART_LCR_SPAR		0x20 /* Stick parity (?) */
#define UART_LCR_EPAR		0x10 /* Even parity select */
#define UART_LCR_PARITY		0x08 /* Parity Enable */
#define UART_LCR_STOP		0x04 /* Stop bits: 0=1 bit, 1=2 bits */
#define UART_LCR_WLEN5		0x00 /* Wordlength: 5 bits */
#define UART_LCR_WLEN6		0x01 /* Wordlength: 6 bits */
#define UART_LCR_WLEN7		0x02 /* Wordlength: 7 bits */
#define UART_LCR_WLEN8		0x03 /* Wordlength: 8 bits */

/*
 * Access to some registers depends on register access / configuration
 * mode.
 */
#define UART_LCR_CONF_MODE_A	UART_LCR_DLAB	/* Configutation mode A */
#define UART_LCR_CONF_MODE_B	0xBF		/* Configutation mode B */

#define UART_MCR	4	/* Out: Modem Control Register */
#define UART_MCR_CLKSEL		0x80 /* Divide clock by 4 (TI16C752, EFR[4]=1) */
#define UART_MCR_TCRTLR		0x40 /* Access TCR/TLR (TI16C752, EFR[4]=1) */
#define UART_MCR_XONANY		0x20 /* Enable Xon Any (TI16C752, EFR[4]=1) */
#define UART_MCR_AFE		0x20 /* Enable auto-RTS/CTS (TI16C550C/TI16C750) */
#define UART_MCR_LOOP		0x10 /* Enable loopback test mode */
#define UART_MCR_OUT2		0x08 /* Out2 complement */
#define UART_MCR_OUT1		0x04 /* Out1 complement */
#define UART_MCR_RTS		0x02 /* RTS complement */
#define UART_MCR_DTR		0x01 /* DTR complement */

#define UART_LSR	5	/* In:  Line Status Register */
#define UART_LSR_FIFOE		0x80 /* Fifo error */
#define UART_LSR_TEMT		0x40 /* Transmitter empty */
#define UART_LSR_THRE		0x20 /* Transmit-hold-register empty */
#define UART_LSR_BI		0x10 /* Break interrupt indicator */
#define UART_LSR_FE		0x08 /* Frame error indicator */
#define UART_LSR_PE		0x04 /* Parity error indicator */
#define UART_LSR_OE		0x02 /* Overrun error indicator */
#define UART_LSR_DR		0x01 /* Receiver data ready */
#define UART_LSR_BRK_ERROR_BITS	0x1E /* BI, FE, PE, OE bits */

#define UART_MSR	6	/* In:  Modem Status Register */
#define UART_MSR_DCD		0x80 /* Data Carrier Detect */
#define UART_MSR_RI		0x40 /* Ring Indicator */
#define UART_MSR_DSR		0x20 /* Data Set Ready */
#define UART_MSR_CTS		0x10 /* Clear to Send */
#define UART_MSR_DDCD		0x08 /* Delta DCD */
#define UART_MSR_TERI		0x04 /* Trailing edge ring indicator */
#define UART_MSR_DDSR		0x02 /* Delta DSR */
#define UART_MSR_DCTS		0x01 /* Delta CTS */
#define UART_MSR_ANY_DELTA	0x0F /* Any of the delta bits! */

#define UART_SCR	7	/* I/O: Scratch Register */

/*
 * DLAB=1
 */
#define UART_DLL	0	/* Out: Divisor Latch Low */
#define UART_DLM	1	/* Out: Divisor Latch High */

/*
 * LCR=0xBF (or DLAB=1 for 16C660)
 */
#define UART_EFR	2	/* I/O: Extended Features Register */
#define UART_XR_EFR	9	/* I/O: Extended Features Register (XR17D15x) */
#define UART_EFR_CTS		0x80 /* CTS flow control */
#define UART_EFR_RTS		0x40 /* RTS flow control */
#define UART_EFR_SCD		0x20 /* Special character detect */
#define UART_EFR_ECB		0x10 /* Enhanced control bit */
/*
 * the low four bits control software flow control
 */

/*
 * LCR=0xBF, TI16C752, ST16650, ST16650A, ST16654
 */
#define UART_XON1	4	/* I/O: Xon character 1 */
#define UART_XON2	5	/* I/O: Xon character 2 */
#define UART_XOFF1	6	/* I/O: Xoff character 1 */
#define UART_XOFF2	7	/* I/O: Xoff character 2 */

/*
 * EFR[4]=1 MCR[6]=1, TI16C752
 */
#define UART_TI752_TCR	6	/* I/O: transmission control register */
#define UART_TI752_TLR	7	/* I/O: trigger level register */

/*
 * LCR=0xBF, XR16C85x
 */
#define UART_TRG	0	/* FCTR bit 7 selects Rx or Tx
				 * In: Fifo count
				 * Out: Fifo custom trigger levels */
/*
 * These are the definitions for the Programmable Trigger Register
 */
#define UART_TRG_1		0x01
#define UART_TRG_4		0x04
#define UART_TRG_8		0x08
#define UART_TRG_16		0x10
#define UART_TRG_32		0x20
#define UART_TRG_64		0x40
#define UART_TRG_96		0x60
#define UART_TRG_120		0x78
#define UART_TRG_128		0x80

#define UART_FCTR	1	/* Feature Control Register */
#define UART_FCTR_RTS_NODELAY	0x00  /* RTS flow control delay */
#define UART_FCTR_RTS_4DELAY	0x01
#define UART_FCTR_RTS_6DELAY	0x02
#define UART_FCTR_RTS_8DELAY	0x03
#define UART_FCTR_IRDA		0x04  /* IrDa data encode select */
#define UART_FCTR_TX_INT	0x08  /* Tx interrupt type select */
#define UART_FCTR_TRGA		0x00  /* Tx/Rx 550 trigger table select */
#define UART_FCTR_TRGB		0x10  /* Tx/Rx 650 trigger table select */
#define UART_FCTR_TRGC		0x20  /* Tx/Rx 654 trigger table select */
#define UART_FCTR_TRGD		0x30  /* Tx/Rx 850 programmable trigger select */
#define UART_FCTR_SCR_SWAP	0x40  /* Scratch pad register swap */
#define UART_FCTR_RX		0x00  /* Programmable trigger mode select */
#define UART_FCTR_TX		0x80  /* Programmable trigger mode select */

/*
 * LCR=0xBF, FCTR[6]=1
 */
#define UART_EMSR	7	/* Extended Mode Select Register */
#define UART_EMSR_FIFO_COUNT	0x01  /* Rx/Tx select */
#define UART_EMSR_ALT_COUNT	0x02  /* Alternating count select */

/*
 * The Intel XScale on-chip UARTs define these bits
 */
#define UART_IER_DMAE	0x80	/* DMA Requests Enable */
#define UART_IER_UUE	0x40	/* UART Unit Enable */
#define UART_IER_NRZE	0x20	/* NRZ coding Enable */
#define UART_IER_RTOIE	0x10	/* Receiver Time Out Interrupt Enable */

#define UART_IIR_TOD	0x08	/* Character Timeout Indication Detected */

#define UART_FCR_PXAR1	0x00	/* receive FIFO threshold = 1 */
#define UART_FCR_PXAR8	0x40	/* receive FIFO threshold = 8 */
#define UART_FCR_PXAR16	0x80	/* receive FIFO threshold = 16 */
#define UART_FCR_PXAR32	0xc0	/* receive FIFO threshold = 32 */

/*
 * These register definitions are for the 16C950
 */
#define UART_ASR	0x01	/* Additional Status Register */
#define UART_RFL	0x03	/* Receiver FIFO level */
#define UART_TFL 	0x04	/* Transmitter FIFO level */
#define UART_ICR	0x05	/* Index Control Register */

/* The 16950 ICR registers */
#define UART_ACR	0x00	/* Additional Control Register */
#define UART_CPR	0x01	/* Clock Prescalar Register */
#define UART_TCR	0x02	/* Times Clock Register */
#define UART_CKS	0x03	/* Clock Select Register */
#define UART_TTL	0x04	/* Transmitter Interrupt Trigger Level */
#define UART_RTL	0x05	/* Receiver Interrupt Trigger Level */
#define UART_FCL	0x06	/* Flow Control Level Lower */
#define UART_FCH	0x07	/* Flow Control Level Higher */
#define UART_ID1	0x08	/* ID #1 */
#define UART_ID2	0x09	/* ID #2 */
#define UART_ID3	0x0A	/* ID #3 */
#define UART_REV	0x0B	/* Revision */
#define UART_CSR	0x0C	/* Channel Software Reset */
#define UART_NMR	0x0D	/* Nine-bit Mode Register */
#define UART_CTR	0xFF

/*
 * The 16C950 Additional Control Register
 */
#define UART_ACR_RXDIS	0x01	/* Receiver disable */
#define UART_ACR_TXDIS	0x02	/* Transmitter disable */
#define UART_ACR_DSRFC	0x04	/* DSR Flow Control */
#define UART_ACR_TLENB	0x20	/* 950 trigger levels enable */
#define UART_ACR_ICRRD	0x40	/* ICR Read enable */
#define UART_ACR_ASREN	0x80	/* Additional status enable */

/*
 * These definitions are for the RSA-DV II/S card, from
 *
 * Kiyokazu SUTO <suto@ks-and-ks.ne.jp>
 */

#define UART_RSA_BASE (-8)

#define UART_RSA_MSR ((UART_RSA_BASE) + 0) /* I/O: Mode Select Register */

#define UART_RSA_MSR_SWAP (1 << 0) /* Swap low/high 8 bytes in I/O port addr */
#define UART_RSA_MSR_FIFO (1 << 2) /* Enable the external FIFO */
#define UART_RSA_MSR_FLOW (1 << 3) /* Enable the auto RTS/CTS flow control */
#define UART_RSA_MSR_ITYP (1 << 4) /* Level (1) / Edge triger (0) */

#define UART_RSA_IER ((UART_RSA_BASE) + 1) /* I/O: Interrupt Enable Register */

#define UART_RSA_IER_Rx_FIFO_H (1 << 0) /* Enable Rx FIFO half full int. */
#define UART_RSA_IER_Tx_FIFO_H (1 << 1) /* Enable Tx FIFO half full int. */
#define UART_RSA_IER_Tx_FIFO_E (1 << 2) /* Enable Tx FIFO empty int. */
#define UART_RSA_IER_Rx_TOUT (1 << 3) /* Enable char receive timeout int */
#define UART_RSA_IER_TIMER (1 << 4) /* Enable timer interrupt */

#define UART_RSA_SRR ((UART_RSA_BASE) + 2) /* IN: Status Read Register */

#define UART_RSA_SRR_Tx_FIFO_NEMP (1 << 0) /* Tx FIFO is not empty (1) */
#define UART_RSA_SRR_Tx_FIFO_NHFL (1 << 1) /* Tx FIFO is not half full (1) */
#define UART_RSA_SRR_Tx_FIFO_NFUL (1 << 2) /* Tx FIFO is not full (1) */
#define UART_RSA_SRR_Rx_FIFO_NEMP (1 << 3) /* Rx FIFO is not empty (1) */
#define UART_RSA_SRR_Rx_FIFO_NHFL (1 << 4) /* Rx FIFO is not half full (1) */
#define UART_RSA_SRR_Rx_FIFO_NFUL (1 << 5) /* Rx FIFO is not full (1) */
#define UART_RSA_SRR_Rx_TOUT (1 << 6) /* Character reception timeout occurred (1) */
#define UART_RSA_SRR_TIMER (1 << 7) /* Timer interrupt occurred */

#define UART_RSA_FRR ((UART_RSA_BASE) + 2) /* OUT: FIFO Reset Register */

#define UART_RSA_TIVSR ((UART_RSA_BASE) + 3) /* I/O: Timer Interval Value Set Register */

#define UART_RSA_TCR ((UART_RSA_BASE) + 4) /* OUT: Timer Control Register */

#define UART_RSA_TCR_SWITCH (1 << 0) /* Timer on */

/*
 * The RSA DSV/II board has two fixed clock frequencies.  One is the
 * standard rate, and the other is 8 times faster.
 */
#define SERIAL_RSA_BAUD_BASE (921600)
#define SERIAL_RSA_BAUD_BASE_LO (SERIAL_RSA_BAUD_BASE / 8)

/*
 * Extra serial register definitions for the internal UARTs
 * in TI OMAP processors.
 */
#define OMAP1_UART1_BASE	0xfffb0000
#define OMAP1_UART2_BASE	0xfffb0800
#define OMAP1_UART3_BASE	0xfffb9800
#define UART_OMAP_MDR1		0x08	/* Mode definition register */
#define UART_OMAP_MDR2		0x09	/* Mode definition register 2 */
#define UART_OMAP_SCR		0x10	/* Supplementary control register */
#define UART_OMAP_SSR		0x11	/* Supplementary status register */
#define UART_OMAP_EBLR		0x12	/* BOF length register */
#define UART_OMAP_OSC_12M_SEL	0x13	/* OMAP1510 12MHz osc select */
#define UART_OMAP_MVER		0x14	/* Module version register */
#define UART_OMAP_SYSC		0x15	/* System configuration register */
#define UART_OMAP_SYSS		0x16	/* System status register */
#define UART_OMAP_WER		0x17	/* Wake-up enable register */
#define UART_OMAP_TX_LVL	0x1a	/* TX FIFO level register */

/*
 * These are the definitions for the MDR1 register
 */
#define UART_OMAP_MDR1_16X_MODE		0x00	/* UART 16x mode */
#define UART_OMAP_MDR1_SIR_MODE		0x01	/* SIR mode */
#define UART_OMAP_MDR1_16X_ABAUD_MODE	0x02	/* UART 16x auto-baud */
#define UART_OMAP_MDR1_13X_MODE		0x03	/* UART 13x mode */
#define UART_OMAP_MDR1_MIR_MODE		0x04	/* MIR mode */
#define UART_OMAP_MDR1_FIR_MODE		0x05	/* FIR mode */
#define UART_OMAP_MDR1_CIR_MODE		0x06	/* CIR mode */
#define UART_OMAP_MDR1_DISABLE		0x07	/* Disable (default state) */

/*
 * These are definitions for the Exar XR17V35X and XR17(C|D)15X
 */
#define UART_EXAR_8XMODE	0x88	/* 8X sampling rate select */
#define UART_EXAR_SLEEP		0x8b	/* Sleep mode */
#define UART_EXAR_DVID		0x8d	/* Device identification */

#define UART_EXAR_FCTR		0x08	/* Feature Control Register */
#define UART_FCTR_EXAR_IRDA	0x08	/* IrDa data encode select */
#define UART_FCTR_EXAR_485	0x10	/* Auto 485 half duplex dir ctl */
#define UART_FCTR_EXAR_TRGA	0x00	/* FIFO trigger table A */
#define UART_FCTR_EXAR_TRGB	0x60	/* FIFO trigger table B */
#define UART_FCTR_EXAR_TRGC	0x80	/* FIFO trigger table C */
#define UART_FCTR_EXAR_TRGD	0xc0	/* FIFO trigger table D programmable */

#define UART_EXAR_TXTRG		0x0a	/* Tx FIFO trigger level write-only */
#define UART_EXAR_RXTRG		0x0b	/* Rx FIFO trigger level write-only */

/*
 * These are definitions for the Altera ALTR_16550_F32/F64/F128
 * Normalized from 0x100 to 0x40 because of shift by 2 (32 bit regs).
 */
#define UART_ALTR_AFR		0x40	/* Additional Features Register */
#define UART_ALTR_EN_TXFIFO_LW	0x01	/* Enable the TX FIFO Low Watermark */
#define UART_ALTR_TX_LOW	0x41	/* Tx FIFO Low Watermark */

#endif /* _LINUX_SERIAL_REG_H */